The present invention relates to a signal aliasing circuit that can be used especially to make a series interpolation cell for an interpolation analog-digital converter. It can be applied for example to converters whose architecture comprises a part known as a series interpolation part requiring high precision.
A French patent application No. 92 14640 describes an analog-digital converter with a folding or aliasing circuit comprising a series interpolation part. One of the useful features of a folding or aliasing analog-digital converter is that it can be used to economize on comparators in its analog part. In particular, the conversion of the signal does not play a role in the comparison of the real amplitude of this signal with the signals from a series of analog comparators. The conversion bits with successive place values are obtained by simple analog combinations depending on how the amplitude of the signal falls within intervals defined by evenly distributed reference voltages, these intervals being increasingly small as and when the conversion bits approach the least significant bit. Thus, a signal Vin is applied to the input of at least two aliasing circuits whose function is to give signals known as xe2x80x9caliasedxe2x80x9d signals Vr1, Vr1b, Vr2, Vr2b with an amplitude that varies with the amplitude of the input signal Vin according to a periodic function having a substantially sinusoidal shape. The functions Vr1 and Vr1b are in phase opposition. Similarly, the functions Vr2 and Vr2b are in phase opposition. The functions Vr1 and Vr2 for their part are in quadrature. The differences (Vr1xe2x88x92Vr1b), (Vr2xe2x88x92Vr2b) periodically cancel each other out for input voltage values that are the above-mentioned reference voltages. From these differences, an interpolation cell sets up signals that have the same general form as the signals set up from the differences in aliased signals, but get cancelled out for input voltage values that are in between the above-mentioned reference voltages. Thus, if an interpolation cell comprises 2n+1 reference voltages as described here above at input, it has 2n+1+1 voltages known as interpolation voltages. A cell therefore enables the creation of an additional information bit. From an initial aliasing circuit, the cascade-connected interpolation cells therefore give the different successive bits corresponding to the conversion of an analog variable, starting with the most significant bit. The interpolation cells are conventionally the cells known as xe2x80x9cGilbert multiplierxe2x80x9d cells described especially in the above-mentioned French patent application as well as in the international application WO 92/08288.
The above short description of an analog-digital converter with aliasing circuit shows how important it is for the reference voltages to be precise. Now, these voltages are obtained in interpolation circuits comprising signal aliasing circuits, especially Gilbert cells, whose principle of operation is based on current shunt operations in pairs of differential arms comprising bipolar transistors or MOS type transistors that are cascade-cabled. In this architecture, it follows that the reference voltages depend especially on the base-emitter voltages Vbe of cascade-connected transistors. This voltage itself depends on the current of the transistors and other external parameters such as for example the temperature. The precision of the reference voltages and therefore of the result of the analog-digital conversion is thereby affected. Furthermore, for a given peak voltage, the cascade of voltages Vbe limits the useful voltage, namely the voltage available for the conversion.
The aim of the invention to overcome the above-mentioned drawbacks by limiting the number of cascaded base-emitter voltages Vbe in the signal aliasing circuit of an interpolation cell. To this end, an object of the invention is a signal aliasing circuit comprising two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair, each group of two parallel-connected transistors being connected by a respective common resistor to a second power supply terminal, the two outputs of the aliasing circuit being the combined collectors of the two groups of parallel-connected transistors.
An object of the invention is also a signal aliasing cell designed to receive four voltages varying as a function of an analog signal Vin, the functions varying as a function of Vin in phase opposition, two by two, and in phase quadrature, two by two, this cell giving at least two aliased output signals varying in phase opposition and having more aliasings than the input voltages for one and the same variation of Vin, the output signal combining the references of the input signals. The cell comprises an aliasing circuit as defined here above wherein the bases of the four transistors receive the four voltages varying as a function of the analog signal Vin.
Yet another object of the invention is an interpolation cell for an interpolation analog-digital converter using cells as defined here above.
The main advantage of the invention is that it increases the conversion speed, raises performance in speed, especially that of the analog-digital converter, without in any way significantly increasing the supply voltages, improves these speed performance characteristics in a simple way, and is simple to implement.